`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module: AUDIO_CLK                                                            //
// Author: Zhiyuan Lin                                                          //
// Date: 3/30/2014                                                              //
// Description: This module is to generate the necessary Clock signals for audio//
//              playback.                                                       //
// Detail: clk_4Hz is the clock to control the beats.                           //
//         clk_6MHz is the reference clock to generate different scales.        //
//////////////////////////////////////////////////////////////////////////////////
module AUDIO_CLK(clk_50MHz, clk_6MHz, clk_4Hz);
    input clk_50MHz;
    output reg clk_6MHz, clk_4Hz;
    //wire clk_50MHz;
    reg [2:0] counter1;
    reg [31:0] counter2;
always @(posedge clk_50MHz) 
  begin 
  if(counter1 == 4) begin   
    counter1 <= 3'b000;     
    clk_6MHz <= ~clk_6MHz ;   
  end 
  else 
  counter1 <= counter1 + 1;
  end
always @(posedge clk_50MHz) 
  begin 
  if(counter2 == 6250000) begin   
  counter2 <= 3'b000;   
  clk_4Hz <= ~clk_4Hz;   
  end 
  else 
  counter2 <= counter2 + 1;
  end
endmodule
